EDN

Aldec releases Active-HDL 7.1

Well known for its mixed-language simulation and advanced design tools for ASIC and FPGA devices, Aldec, Inc., has announced the release of Active-HDL 7.1. Active-HDL 7.1 is an FPGA and ASIC design ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Design-Reuse

Aldec Enhances Award-Winning Active-HDL with Flexible File Management to Manage Complex FPGA Projects

Henderson, NV – September 24, 2012 – Aldec, Inc. today announced the immediate availability of Active-HDL™ 9.2, an HDL-based FPGA Design and Simulation solution now offering flexible file ...
Semiconductor Engineering

Linting With ALINT-PRO Within Active-HDL

Active-HDL suggests an early-bug-detection flow via the integration with ALINT-PRO. The Active-HDL user has an access to both different linting methodologies supported by ALINT-PRO: full chip-level ...
EDN

Active-HDLTM provides advanced verification environment for all QuickLogic FPGA and ESP families

QuickLogic Corporation and Aldec, Inc.,announced that QuickLogic is integrating Aldec's Active-HDLTM Lite verification environment into its QuickWorks QuickLogic and Aldec have partnered to provide ...
Business Wire

Aldec Releases Active-HDL 10.1 with 64-bit Simulation Support

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design ...
Electronic Design

Graphical Code Coverage Tool Speeds Design Debugging

Code Snooper, a code coverage software tool for use with the Active-HDL design and verification environment is integrated with the Active-HDL simulation kernel and does not require additional ...
New Electronics

Aldec enhances Active-HDL to support new features

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has announced that it has enhanced Active-HDL to support new features within ...
New Electronics

Aldec platform supports newest fpga devices

Electronic design verification specialist, Aldec has launched an HDL based fpga design and simulation platform that supports the newest fpga devices. According to Aldec, Active-HDL version 9.1 is a ...
Electronic Design

Mixed-Language Simulator Serves FPGA Designers

In the Active-HDL Designer Edition, a low-cost mixed-language RTL simulator, designers gain a high-performance simulator for designs targeted at FPGAs. Basically, FPGA designers have been forced to ...
Design-Reuse

Aldec's Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

Henderson, USA – December 3, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...