Well known for its mixed-language simulation and advanced design tools for ASIC and FPGA devices, Aldec, Inc., has announced the release of Active-HDL 7.1. Active-HDL 7.1 is an FPGA and ASIC design ...
HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
SAN FRANCISCO — Aldec Inc. has released a new version of its Active-HDL 7.1 FPGA and ASIC design entry and verification platform, including several new tools. Aldec (Henderson, Nev.) said new tools ...
Henderson, NV – September 24, 2012 – Aldec, Inc. today announced the immediate availability of Active-HDL™ 9.2, an HDL-based FPGA Design and Simulation solution now offering flexible file ...
Active-HDL suggests an early-bug-detection flow via the integration with ALINT-PRO. The Active-HDL user has an access to both different linting methodologies supported by ALINT-PRO: full chip-level ...
HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design ...
Code Snooper, a code coverage software tool for use with the Active-HDL design and verification environment is integrated with the Active-HDL simulation kernel and does not require additional ...
Electronic design verification specialist, Aldec has launched an HDL based fpga design and simulation platform that supports the newest fpga devices. According to Aldec, Active-HDL version 9.1 is a ...
Results that may be inaccessible to you are currently showing.
Hide inaccessible results