EDN

Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology

SAN JOSE, Calif., May 3 /PRNewswire/ — Xilinx (Nasdaq: XLNX) today introduced the ISE® Design Suite 12 software to enable breakthrough optimizations for power and cost with greater design productivity ...
EDN

Xilinx ISE 12 adds intelligent clock gating

SAN FRANCISCO—Xilinx Inc. Monday (May 3) introduced a new version of its ISE Design Suite to support its Virtex-6 and Spartan-6 FPGA families. According to the company, ISE 12 adds intelligent clock ...
Semiconductor Engineering

Smarter Clock Gating

With the proliferation of mobile devices, power consumption and battery life have emerged as significant concerns during chip design. There are many different techniques used for power optimization, ...
Semiconductor Engineering

Clean Your Clock

Lowering power consumption seems to be on every designer’s mind these days. And yet when asked about applying low-power design techniques, many engineers respond, “Well, we do clock gating … and ...