One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles ...

Some brief theory and typical measurements of phase noise. How to produce the lowest phase noise at a PLL output. A standard design procedure for a typical Type 2, second-order loop. As stated in ...

The purpose of a phase locked loop (PLL) is to generate a frequency and phase-locked output oscillation signal. To achieve this goal, prior art essentially functioned ...

The clever trick comes by dividing the output frequency. For example, a 100 MHz crystal oscillator is difficult to design. But taking a voltage-controlled oscillator at 100 MHz (nominal) and dividing ...

For an IC building block that came into being at about the same time as the microprocessor in the late 1960s and early 1970s, the “lowly” phase-locked loop has not done too badly. The hidden beauty of ...

The NB4N507A is a fully integrated phase lock loop (PLL) designed to replace expensive crystal oscillators for clock generation in a variety of consumer and networking applications. The IC generates a ...

Delay-locked loops (DLLs) are critical components in modern electronic systems, providing robust synchronisation of clock signals in a variety of applications ranging from high-speed communication to ...

This application note details the design of a complete 12GHz, ultra-low phase noise fractional-N phase locked loop (PLL) with external VCO. It consists of a high performance fractional-N PLL (MAX2880) ...

Related to my search for reduced motor noise (and thanks to all who have made suggestions – ‘scope avaunt this weekend), is a search for speed stability in that motor*. And to someone who is in love ...

When Hackaday runs a contest, we see all manner of clever projects. But inevitably there are some we don’t see, because their builders didn’t manage to get them finished in time. [Park Frazer]’s phase ...