EDN

Xilinx Improves Design Flow for Industry’s Only Proven Partial Reconfiguration FPGA Technology with ISE Design Suite 12.2

SAN JOSE, Calif., July 27 /PRNewswire/ –Xilinx, Inc. (Nasdaq: XLNX) today announced the availability of its fourth generation partial reconfiguration design flow and new improvements to its ...
Electronic Design

Xilinx And Synopsys Collaborate On Tool Flow For Platform FPGAs

Time-saving verification tools have been added to an advanced tool flow for high-end FPGA design. The flow, a collaboration between Xilinx Inc. of San Jose and Synopsys Inc. of Mountain View, Calif., ...
EDN

Xilinx, AccelChip deliver integrated DSP design flow

SAN Francisco, Calif. — AccelChip announced a development agreement with Xilinx, under which Accelchip will integrate its DSP Synthesis tool with Xilinx's System Generator design environment. The ...
Design-Reuse

Xilinx Planahead v2.2 Tool Delivers Up To 2X Performance Boost And 50% Design Cycle Reduction For Virtex-4 FPGAs

New release of PlanAhead floorplanner now supports Virtex-4 devices, the industry's highest density, highest speed FPGA family shipping on 90nm technology SAN JOSE, Calif., January 12, 2005 - Xilinx, ...