Semiconductor Engineering

Graph-Based, Formal Equivalence Checking Method

A new research paper titled “Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits” was published by researchers at University of Bremen and DFKI GmbH. “Due to the increasing ...
EDN

Sequential equivalence checking for RTL models

In this paper, we examine the need for formal sequential equivalence checkingacross pairs of RTL models. We present scenarios that call for modifying thesequential behavior of RTL models while ...
EDN

A Brief History of Formal Verification

As conventional simulation-based testing has increasingly struggled to cope with design complexity, strategies centered around formal verification have quietly evolved In this article, I review the ...
Design-Reuse

Experiences in Formal Checking of a DSP IP Core

This paper describes an experience in applying formal techniques to the verification of system IP cores for a Telecom System on Chip. We discuss the application methods and highlight the complementary ...
Semiconductor Engineering

Equivalence Checking

Everyone is consumed by power these days. The less power our devices use, the better—the longer our batteries will last, the more applications we can use simultaneously, the less HVAC capacity is ...
Nature

Formal Methods for Software

Formal methods constitute a suite of mathematically based techniques that are employed to specify, develop, and verify software systems with a high degree of rigour. These techniques aim to transform ...
Design-Reuse

Sequential equivalence checking for RTL models

In this paper, we examine the need for formal sequential equivalence checking across pairs of RTL models. We present scenarios that call for modifying the sequential behavior of RTL models while ...